Who are we and what do we do? The HVP team in TI develops power solutions for a wide array of end-equipments, with several hundreds of volts of withstand capability. This team in TI offers one of the world's largest comprehensive portfolios of high-performance AC/DC and isolated DC/DC controllers, GaN-integrated power-stages and converters, and modules with the widest range of power topology options. This is a new investment area for TI in India, and the candidate will get to be part of an exciting startup-like ecosystem, getting the experience of building a team and technical expertise under the safety of the wider TI umbrella. What will you be doing in this role? (Responsibilities) Responsible to develop detailed coverage driven Verification plan working closely with System and design team. Behavioral Modelling of analog blocks using SV RNM, verilogAMS (wreal, electrical). Identify and develop system level tests in AMS to ensure bug free silicon. Independently develop SV/UVM based testbenches, tests, checkers, assertions and enhancing with randomization and coverage. Innovate & drive new and improved design verification methodologies as needed, work with the EDA team to upgrade tools and flows. Interacting with Test/Validation in various post silicon activities and customer debug/analysis. Team player: Collaborate and drive smart initiatives within the team. Mentor and lead the junior folks in team Closely working with DMS/DV team to understand the SOC – RTL verification and capable to support in case of project requirement. Good interaction with Digital Design team, Firmware developers, Analog Designers, and rest of the team. What do we expect from you? (Mini Qualifications) Knowledge and Skills Strong fundamentals in mixed-signal designs, including a thorough understanding of analog building blocks, digital design processes, and top-level integration. Experienced in developing mixed signal testbench in SV/UVM from scratch with the capability to debug and optimize mixed-signal simulation performance, understanding the necessary trade-offs. Strong simulation debug capability, able to analyze simulation waveforms and pinpoint issues in schematics simulation or models Knowledge on analog controllers to develop system testbench and debug issues. Handling & owning design deliverables and schedule Bachelors / Masters in Electrical / Electronics Engineering Other Good team player, attitude and thirst for continuous learning Strong communication and interpersonal skills Ability to function independently, be self-driven Preferred Skills/ Experience 3-10 years of experience in mixed-signal design verification Hands on experience/expertise in working with SOC and developing SOC-AMS testbench. Expertise in developing the simulation/DV plan as per the system definition. Experience with Cadence Mixed-Signal Design Environment tools, including Virtuoso, ADE Assembler, Xcelium, VIVA & Simvision Expertise in Cadence Spectre simulation test bench development, Regression Flow & debug Expertise in mixed-signal waveform review, debugging, and coverage analysis. Excellent with HDL – system Verilog, UVM, verilogAMS Experience in writing checkers, assertions and monitors for top-level simulations. Expertise in automation using Python / Perl / Tcl / shell scripting. Experience as AMS Lead for a project is an addon.