Analog layout engineer

Analog Layout Engineer

Location: Bengaluru

Experience: 4–10 Years

Role Overview

We are looking for a hands-on Analog Layout Engineer with strong experience in advanced-node custom layout for analog/mixed-signal IPs. The role involves ownership of layout implementation, optimization, physical verification, and signoff for next-generation semiconductor designs.

Key Responsibilities

Execute custom analog/mixed-signal layout from schematic to signoff. Work on advanced nodes: 2nm, 3nm, 5nm, Fin FET. Implement matching-critical layouts using common-centroid, interdigitation, symmetry, shielding, guard rings, and dummy structures. Optimize area, parasitics, matching, performance, and reliability. Drive DRC/LVS/ERC/PEX closure and resolve physical verification issues. Collaborate closely with Circuit Design, Physical Verification, CAD, and Technology teams. Support post-layout extraction and simulation and address layout-dependent performance issues.

Core Technical Requirements

4–10 years of hands-on Analog/Custom Layout experience. Strong expertise in advanced-node layout and Fin FET technologies. Proficiency in Cadence Virtuoso or equivalent custom layout tools. Strong understanding of DRC, LVS, ERC, PEX, parasitic extraction, and signoff. Experience with complex analog/mixed-signal blocks. Strong understanding of device matching, layout-dependent effects, and advanced-node design rules.