CPU RTL Design Engineer

Key Responsibilities: Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU. Participate in defining the architecture and microarchitecture features of the CPU design. Write RTL and optimize logic for power, performance, area, and timing goals. Ensure design integrity for physical implementation through effective strategies, tools, and methods. Review verification plans to ensure design features are correctly validated and resolve failing RTL tests. Document microarchitectural specifications (MAS) for the CPU features. Collaborate with SoC customers to ensure seamless integration and high-quality performance of the CPU block. Minimum Qualifications: 7 years experience in RTL design using Verilog, V2K, or System Verilog, with strong knowledge of hardware modeling and logic debug environments. 5 years experience with modern energy-efficient and low-power logic design methods, including techniques applicable to high-frequency optimization. 5 years experience in Cross-clock domain crossings and power aware design. 3 years experience in scripting languages such as TCL, Perl, or Python. Preferred Qualifications: Knowledge on CPU power-management namely power/electrical budgeting, dynamic voltage and frequency scaling, thermal, P/C states and reset sequence handling. Comprehensive knowledge of Intel Architecture ISA and system architecture, including x86 assembly language. Experience with high-speed circuit design and optimization, specifically for datapath, circuits, and arrays. Familiarity with circuit planning and timing convergence processes. Ability to leverage broad understanding of CPU architecture to deliver impactful solutions. Proficient with static timing analysis, UPF and lint checks. Good communication skills.