Senior DFT Engineer – Bangalore
Experience: 3+ Years
Location: Bangalore
Key Responsibilities:
Design and implement DFT solutions for complex So C designs. Hands-on experience in Scan, ATPG, MBIST, JTAG and DFT DRC/debug. Perform scan insertion, ATPG pattern generation, fault coverage analysis and optimization. Experience with MBIST insertion, verification, pattern generation and debug. Debug DFT simulations, tester failures and support silicon bring-up/post-silicon debug. Collaborate with RTL, Design, Verification and Physical Design teams. Contribute to DFT flow automation and methodology improvements.Required Skills :
Strong understanding of ASIC/So C DFT flow and methodologies. Hands-on experience with Tessent / Tetra MAX / Test MAX / Synopsys SMS. Good knowledge of ATPG, Scan, MBIST, JTAG, IEEE 1500 and OCC. Experience with VCS / Verdi / Xcelium / Questa simulation and debug. Knowledge of Verilog/System Verilog. Scripting skills in TCL / Perl / Python. Strong debugging, analytical and problem-solving skills.Education: B. E./B. Tech/M. E./M. Tech in ECE, Electrical & Electronics, or VLSI.
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