Lead sta & synthesis engineer

Lead STA & Synthesis Engineer

Location: Bengaluru

Experience: 8–12 Years

Role Overview

We are looking for a Lead STA & Synthesis Engineer with strong hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex So C designs.

Key Responsibilities

Own RTL-to-gate synthesis and timing analysis for complex So C/IP designs. Drive STA, timing constraints, and timing closure across MCMM/MMC scenarios. Develop, validate, and debug SDC constraints, clocks, exceptions, and timing paths. Perform setup/hold analysis, critical path analysis, and timing optimization. Work closely with RTL, Physical Design, DFT, and implementation teams to resolve timing issues. Analyze and optimize area, power, and performance (PPA) during synthesis. Drive ECOs and timing fixes through implementation and signoff. Debug synthesis/STA issues including unconstrained paths, false paths, clock interactions, and constraint violations. Develop scripts and automation using Tcl/Python/Perl to improve flow efficiency.

Core Technical Requirements

8–12 years of experience in STA, synthesis, or front-end implementation. Strong expertise in Synopsys Design Compiler / Fusion Compiler or equivalent synthesis tools. Strong hands-on experience with Synopsys Prime Time or equivalent STA tools. Deep understanding of SDC, MCMM/MMC, setup/hold, clocking, OCV/AOCV/POCV, and timing exceptions. Experience with RTL synthesis, timing optimization, and ECO flows. Strong understanding of ASIC/So C implementation and signoff methodologies. Proficiency in Tcl/Python/Perl scripting. Experience with advanced technology nodes and complex So C designs is preferred.