Senior Analog Layout Engineer Experience: 5 years, Location: Bangalore, Employment Type: Full-Time (Onsite) About the Role We are looking for a Senior Analog Layout Engineer to design and implement high-performance layouts for analog, mixed-signal, and RF integrated circuits. You will work closely with circuit designers, product engineers, and process/reliability teams to deliver silicon-proven layouts that meet aggressive performance, area, and schedule targets. Key Responsibilities Own full-chip and block-level layout for analog/mixed-signal Ips like ADCs/DACs, bandgaps, LDOs, amplifiers, comparators. Translate schematics into layout while optimizing for matching, parasitics, noise isolation, and electromigration/IR drop. Perform floorplanning, place & route strategy, and top level integration for mixed-signal blocks. Work closely with circuit designers to understand design intent and apply appropriate layout techniques (symmetry, common centroid, guard rings, shielding). Run and debug DRC, LVS, ERC, and parasitic extraction (PEX); close all physical verification checks. Collaborate with design for reliability and design for manufacturing teams to ensure layout meets EM/IR, ESD, and antenna rules. Support post layout simulation correlation and help debug silicon issues related to layout. Mentor junior layout engineers and contribute to layout methodology, automation scripts, and best-practice documentation. Interface with foundry/PDK teams on process design kit updates and technology qualification. Required Qualifications Bachelor's or Master's degree in Electrical Engineering, Microelectronics. 5 years of hands-on analog/mixed-signal IC layout experience. Strong expertise in Cadence Virtuoso (or similar layout tools); experience with Calibre or equivalent for DRC/LVS/PEX. Solid understanding of analog layout techniques: matching, symmetry, shielding, guard-ringing, ESD, and noise-sensitive routing. Familiarity with parasitic-aware layout and post-layout simulation correlation. Strong understanding of EM/IR, antenna rules, and reliability driven layout practices. Good communication skills and ability to work cross functionally with design, verification, and product teams. Full chip experience preferred Interested candidates can send their CVs to
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