Functional verification engineer

Job Title: Functional Verification Engineer
Location: Bangalore
Experience: 4+ Years
Job Type: Full-time
Industry: Semiconductor / VLSI / ASIC Design
Education: B. E./B. Tech or M. E./M. Tech in ECE/EEE/Computer Engineering
Job Description:
We are seeking a skilled and detail-oriented Functional Verification Engineer to be part of our IP/So C verification team. The candidate will be responsible for verifying complex digital designs using industry-standard methodologies to ensure functional correctness and high-quality silicon delivery.
Key Responsibilities:
Develop and execute verification test plans based on design specifications and architecture.
Design and implement testbenches using System Verilog and UVM methodology.
Create constrained-random and directed test cases.
Build verification components (agents, monitors, scoreboards, checkers).
Perform coverage analysis (code and functional) and close coverage gaps.
Debug simulation failures and work closely with design and architecture teams.
Conduct regressions and analyze results for functional and performance issues.
Document test plans, verification environments, and test results.
Participate in design and verification reviews.
Required Skills:
4+ years of hands-on experience in functional verification of IP/So C.
Strong knowledge and working experience with System Verilog and UVM.
Familiarity with RTL design (Verilog/VHDL).
Experience in coverage-driven verification, assertions, and functional coverage closure.
Proficient in using simulators like VCS, Questa, or Incisive.
Good scripting skills in Perl, Python, or Shell for automation.
Strong debugging skills using simulation waveform viewers.
Good understanding of common protocols such as AXI, AHB, APB, PCIe, USB, etc
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