Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 6–8 years of experience in SoC or subsystem design. Strong knowledge of ARM architecture, AMBA protocols (AXI, AHB, APB), and system-level integration. Hands-on experience with Arm Corestone-based packages or similar ARM reference designs. Solid experience in ASIC front-end design, including RTL development and integration flows. Proficiency in Static Timing Analysis using Primetime or Cadence tools. Experience in ASIC synthesis, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) techniques using Spyglass. Familiarity with low-power design techniques, UPF, and tools like PowerArtist or Power Compiler (a plus). FPGA prototyping experience is desirable. Strong debugging skills across simulation, lint, CDC, and synthesis environments. Ability to collaborate in a fast-paced, cross-functional engineering environment
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